Two's Complement & Signed Arithmetic

Positional notation only covers non-negative values. To represent negative numbers, almost every modern architecture uses a specific encoding: two's complement.

Signed integers: two's complement

Unsigned binary can only represent non-negative numbers. Two's complement lets addition and subtraction use the same hardware adder regardless of sign, which is why it won out over older schemes like sign-magnitude or one's complement.

To negate a number in two's complement: invert every bit, then add 1.

  00000101   (5, 8-bit)
  11111010   (invert)
+ 00000001   (add 1)
-----------
  11111011   (-5, 8-bit two's complement)

The most significant bit acts as a sign indicator, but it is still a weighted bit — for an 8-bit signed value it has a weight of -128 rather than +128. That single change in weight is the entire trick behind two's complement.

#include <stdint.h>
 
int8_t a = 5;
int8_t b = -5;
 
// At the bit level: 00000101 + 11111011 = 100000000
// Truncated to 8 bits: 00000000 -> 0, as expected.
int8_t sum = a + b;

Overflow

Overflow happens when a result can't be represented in the available bit width. For signed addition, overflow occurs precisely when two operands of the same sign produce a result with the opposite sign. Hardware exposes this as a dedicated overflow flag (V in most ISAs), distinct from the carry flag used for unsigned arithmetic — conflating the two is a common source of subtle bugs when implementing arbitrary-precision arithmetic by hand.

Why this matters in practice

• Integer overflow bugs in firmware are almost always a two's complement or bit-width mismatch hiding in plain sight.
• Compilers and debuggers report signed/unsigned mismatches because the same bit pattern means a different value depending on how it's interpreted.

Once positional notation and two's complement are second nature, the next step is seeing how these bit patterns are manipulated by physical hardware — which is exactly where the Digital Logic Design lesson picks up.